Logic systems of the single ended cascode voltage switch type are described in commonly assigned U.S. patent application having Ser. No. 554,148 filed by W. R. Griffin and L. G. Heller on even date. These circuits are generally made in the complementary metal oxide semiconductor (CMOS) technology having an N channel transistor, or NMOS, matrix as a logic system with a P channel transistor, or PMOS, matrix as a complementary logic network.
Another of the cascode voltage switch type logic circuits, but of a differential type, is disclosed in commonly assigned U.S. patent application Ser. No. 508,454, filed by J. W. Davis and N. G. Thoma on June 27, 1983. This differential logic circuit includes cross-coupled P channel load devices coupled to complementary outputs of an NMOS logic network.
In an article in 1981 IEEE International Solid-State Circuits Conference, Feb. 20, 1981, pp. 230, 231 and 276 by B. T. Murphy et al entitled "A CMOS 32b Single Chip Microprocessor" and also in an article in IEEE Journal of Solid-State Circuits, Vol. SC-17, No. 3, June 1982, by R. H. Krambeck et al entitled "High-Speed Compact Circuits with CMOS" there is disclosed single-ended clocked dynamic CMOS logic circuits which include a P channel device as a load connected to an NMOS logic network with an inverter connected between an output terminal and the P channel load device.
It should be noted that the above referenced Murphy et al and Krambeck et al logic circuits cannot be used to provide a complete logic family.